pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 363

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

ECM
SSD0
XAIS
User’s Manual
Hardware Description
Error Counter Mode
The function of the error counters (FEC,CEC,CVC,EBC) is
determined by this bit.
0 =
1 =
Select System Date Rate 0
SIC1.SSD1, FMR1.SSD0 and SIC2.SSC2 define the data rate on the
system highway. Programming SSD1/SSD0 and corresponding data
rate is shown below.
SIC2.SSC2 = 0:
00 =
01 =
10 =
11 =
SIC2.SSC2 = 1:
00 =
01 =
10 =
11 =
Transmit AIS Towards Remote End
Sends AIS (blue alarm) on ports XL1, XL2 towards the remote end.
If Local Loop Mode is enabled the transmitted data is looped back to
the system internal highway without any changes.
Before reading an error counter the corresponding bit in the
Disable Error Counter register (DEC) has to be set. In 8 bit
access the low byte of the error counter should always be read
before the high byte. The error counters are reset with the rising
edge of the corresponding bits in the DEC register.
Every second the error counter is latched and then
automatically reset. The latched error counter state should be
read within the next second. Reading the error counter during
updating should be avoided (do not access an error counter
within 1 µs after the one-second interrupt occurs).
2.048 Mbit/s
4.096 Mbit/s
8.192 Mbit/s
16.384 Mbit/s
1.544 Mbit/s
3.088 Mbit/s
6.176 Mbit/s
12.352 Mbit/s
363
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56