pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 351
pef2256e
Manufacturer Part Number
pef2256e
Description
E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF2256E.pdf
(518 pages)
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HDLCI
Receive Address Byte High Register 1 (Read/Write)
Value after reset: FD
RAH1
In operating modes that provide high byte address recognition, the high byte of the
received address is compared to the individually programmable values in RAH1 and
RAH2.
RAH1
Receive Address Byte High Register 2 (Read/Write)
Value after reset: FF
RAH2
RAH2
Receive Address Byte Low Register 1 (Read/Write)
Value after reset: FF
RAL1
User’s Manual
Hardware Description
7
7
7
Inverse HDLC Operation - HDLC Channel 1
Setting this bit selects the HDLC channel 1 operation mode.
0 =
1 =
Value of the First Individual High Address Byte
Bit 1 (C/R-bit) is excluded from address comparison.
Value of Second Individual High Address Byte
H
H
H
Normal operation, HDLC attached to line side
Inverse operation, HDLC attached to system side.
HDLC data is received on XDI and transmitted on RDO.
Transmit time slot configuration is done in RTR(4:1), receive
time slot configurarion is done in TTR(4:1).
351
1
0
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
0
0
0
FALC
(04)
(05)
(06)
®
56
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