pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 49

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

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The FALC
controlled by an external microprocessor or microcontroller. The functional block
diagram is shown in
The main interfaces are
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as well as several control lines for reset and clocking purpose.
The main internal functional blocks are
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User’s Manual
Hardware Description
Receive and transmit line interface
PCM system highway interface/H.100 bus
Microprocessor interface
Boundary scan interface
Analog line receiver with equalizer network and clock/data recovery
Analog line driver with programmable pulse shaper and line build out
Central clock generation module
Elastic buffers for receive and transmit direction
Receive Framer, receive line decoding, alarm detection, PRBS and performance
monitoring
Transmit framer, receive line encoding, alarm and PRBS generation
Receive jitter attenuator
Transmit jitter attenuator
Three HDLC controllers (one of them including SS7 and BOM support) and CAS
signaling controller
Test functions (loop switching local - remote - payload - single channel)
Register access interface
Boundary scan control
®
Functional Description E1/T1/J1
Functional Overview
56 device contains analog and digital function blocks that are configured and
Figure
5.
49
Functional Description E1/T1/J1
DS1.1, 2003-10-23
PEF 2256 H/E
FALC
®
56