pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 229

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

Mode Register (Read/Write)
Value after reset: 00
MODE
MDS(2:0)
HRAC
DIV
1)
User’s Manual
Hardware Description
CCR2.RADD must be set, if SS7 mode is selected
MDS2
7
Note: If SCLKX is used to clock the transmission path, commands to
Mode Select - HDLC Channel 1
The operating mode of the HDLC controller is selected.
000 = Reserved
001 = Signaling System 7 (SS7) support
010 = One-byte address comparison mode (RAL1,2)
011 = Two-byte address comparison mode (RAH1,2 and RAL1,2)
100 = No address comparison
101 = One-byte address comparison mode (RAH1,2)
110 = Reserved
111 = No HDLC framing mode
Receiver Active - HDLC Channel 1
Switches the HDLC receiver to operational or inoperational state.
0 =
1 =
Data Inversion - HDLC Channel 1
Setting this bit inverts the internal generated HDLC channel 1 data
stream.
0 =
1 =
MDS1
H
Normal operation, HDLC data stream not inverted
HDLC data stream inverted
Receiver inactive
Receiver active
high clock rate in comparison with the FALC
recommended that bit SIS.CEC should be checked before
writing to the CMDR register to avoid any loss of commands.
the HDLC transmitter should only be sent while this clock is
available. If SCLKX is missing, the command register is
blocked after an HDLC command is given.
MDS0
229
HRAC
DIV
1)
HDLCI
DS1.1, 2003-10-23
®
PEF 2256 H/E
56's clock, it is
E1 Registers
0
FALC
(03)
®
56