pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 459

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

RDO2
CRC162
RAB2
HA12, HA02
User’s Manual
Hardware Description
Note:Shorter frames are not reported.
Receive Data Overflow - HDLC Channel 2
A data overflow has occurred during reception of the frame.
Additionally, an interrupt can be generated
(refer to ISR4.RDO2/IMR4.RDO2).
CRC16 Compare/Check - HDLC Channel 2
0 =
1 =
Receive Message Aborted - HDLC Channel 2
This bit is set, if more than 5 contiguous 1-bits are detected.
High Byte Address Compare - HDLC Channel 2
Significant only if 2-byte address mode is selected.
In operating modes which provide high byte address recognition, the
FALC
of two individually programmable registers (RAH1, RAH2) and the
fixed values FE
Depending on the result of this comparison, the following bit
combinations are possible:
00 = RAH2 has been recognized
01 = Broadcast address has been recognized
10 = RAH1 has been recognized C/R=0 (bit 1)
11 = RAH1 has been recognized C/R=1 (bit 1)
Note:If RAH1, RAH2 contain identical values, a match is indicated by
• MDS2(2:0) = 010 (8 bit Address),
RCRC2=0 : 3 bytes; RCRC2=1 : 2 or 3 bytes
CRC check failed; received frame contains errors.
CRC check o.k.; received frame is error-free.
"10" or "11".
®
compares the high byte of a 2-byte address with the contents
H
and FC
459
H
(broadcast address).
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56