pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 444

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

LA
Receive Byte Count Low - HDLC Channel 1 (Read)
Together with RBCH, bits RBC(11:8), indicates the length of a received frame (1 to 4095
bytes). Bits RBC(4:0) indicate the number of valid bytes currently in RFIFO. These
registers must be read by the CPU following a RME interrupt.
Received Byte Count High - HDLC Channel 1 (Read)
OV
RBC(11:8)
User’s Manual
Hardware Description
Low Byte Address Compare - HDLC Channel 1
Significant in HDLC modes only.
The low byte address of a 2-byte address field, or the single address
byte of a 1-byte address field is compared to two registers. (RAL1,
RAL2).
0 =
1 =
Note:Not valid in SS7 mode. Bit LA has to be ignored, if SS7 mode is
Counter Overflow - HDLC Channel 1
More than 4095 bytes received.
Receive Byte Count - HDLC Channel 1 (most significant bits)
Together with RBCL (bits RBC(7:0)) indicates the length of the
received frame.
RAL2 has been recognized
RAL1 has been recognized
selected.
444
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56