pef2256e Infineon Technologies Corporation, pef2256e Datasheet - Page 374

• Manufacturer Part Number: pef2256e
• Description: E1/t1/j1 Framer And Line Interface Component For Long- And Short-haul Applications
• Manufacturer: Infineon Technologies Corporation

CRCI
XCRCI
RDIS
RCO(10:8)
User’s Manual
Hardware Description
Release
Depending on the selected multiframe format the alarm is reset when
FALC
– the "bit 2 = 0" condition for three consecutive pulse frames
– the "FS-bit" condition for three consecutive multiframes (F12),
– the "DL pattern" for three times in a row (ESF).
Automatic CRC6 Bit Inversion
If set, all CRC bits of one outgoing extended multiframe are inverted
in case a CRC error is flagged for the previous received multiframe.
This function is logically ored with RC0.XCRCI.
Transmit CRC6 Bit Inversion
If set, the CRC bits in the outgoing data stream are inverted before
transmission. This function is logically ored with RC0.CRCI.
Receive Data Input Sense
Digital interface, dual-rail:
0 =
1 =
Digital Interface, CMI:
0 =
1 =
Receive Offset/Receive Frame Marker Offset
Depending on the RP(A to D) pin function different offsets can be
programmed. The SYPR and the RFM pin function cannot be
selected in parallel.
Receive Offset (PC(4:1).RPC(2:0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active.
Calculation of delay time T (SCLKR cycles) depends on the value X
of the receive offset register RC(1:0). Refer to register RC1.
(all formats if selected),
®
Inputs RDIP/RDIN are active low
Inputs RDIP/RDIN are active high
Input ROID is active high
Input ROID is active low
56 does not detect
374
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
FALC
®
56