AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 124

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
5.26
Pin Attribute
Pin Location
Summary
Driven
106
HLDA (Hold Acknowledge)
Output
AJ-03
When HOLD is sampled asserted, the processor completes the
current bus cycles, floats the processor bus, and asserts HLDA
in an acknowledgment that these events have been completed.
The processor does not assert HLDA until the completion of a
locked sequence of cycles. While HLDA is asserted, another bus
master can drive cycles on the bus, including inquire cycles to
the processor. The following signals are floated when HLDA is
asserted: A[31:3], ADS #, ADSC #, AP, BE[7:0]#, CACHE #,
D[63:0], D/C #, DP[7:0], LOCK #, M/IO #, PCD, PWT, SCYC, and
W/R#.
The processor is designed so that HLDA does not glitch.
HLDA is always driven except in the three-state test mode. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY # of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HLDA is
negated one clock edge after the clock edge on which HOLD is
sampled negated.
The assertion of HLDA is independent of the sampled state of
BOFF#.
The processor floats the bus every clock in which HLDA is
asserted.
Preliminary Information
Signal Descriptions
22529B/0—January 2000
Chapter 5