AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 28

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
Scheduler/Instruction
Control Unit
Registers
10
The three types of decodes have the following characteristics:
Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 operations are delivered to the scheduler
for dispatching to the execution units.
The centralized scheduler or buffer is managed by the ICU. The
ICU buffers and manages up to 24 RISC86 operations at a time.
This equals from 6 to 12 x86 instructions. This buffer size (24) is
perfectly matched to the processor’s six-stage RISC86 pipeline,
four RISC86-operations decode rate, and ten parallel execution
units.
The scheduler accepts as many as four RISC86 operations at a
time from the decoders and retires up to four RISC86
o p e ra t i o n s p e r c l o c k cy c l e . T h e I C U i s c a p a b l e o f
simultaneously issuing up to six RISC86 operations at a time to
the execution units. This consists of the following types of
operations:
When managing the RISC86 operations, the ICU uses 69
p hy s i c a l re g i s t e rs c o n t a i n e d w i t h i n t h e R I S C 8 6
microarchitecture.
Short decodes—x86 instructions that are less than or equal
to seven bytes long
Long decodes—x86 instructions less than or equal to 11
bytes long
Vector decodes—complex x86 instructions
Memory load operation
Memory store operation
Complex integer, MMX, or 3DNOW! register operation
Simple integer register operation
Floating-point register operation
Branch condition evaluation
Forty-eight of the physical registers are located in a general
register file.
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Twenty-four of these are rename registers.
The other twenty-four are committed or architectural
registers, consisting of 16 scratch registers and 8 registers
Preliminary Information
Internal Architecture
22529B/0—January 2000
Chapter 2