AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 63

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
UC/WC Cacheability
Control Register
(UWCCR)
.
Figure 37. UC/WC Cacheability Control Register (UWCCR)
Processor State
Observability
Register (PSOR)
Figure 38. Processor State Observability Register (PSOR)
Chapter 3
Symbol
63
63
Reserved
NOL2
STEP
BF
Physical Base Address 1
Symbol
UC1
WC1
No L2 Functionality
Processor Stepping
Bus Frequency Divisor
Description
Uncacheable Memory Type
Write-Combining Memory Type
Description
49
MTRR1
The AMD-K6-2E processor provides two variable-range Memory
Type Range Registers (MTRRs)—MTRR0 and MTRR1—that
each specify a range of memory. Each range can be defined as
uncacheable (UC) or write-combining (WC) memory. Figure 37
shows the format of the UWCCR register. For more detailed
information about the MTRR0, MTRR1, and UWCCR registers,
see “Memory Type Range Registers” on page 207.
The AMD-K6-2E processor provides the processor state
observability register (PSOR) (see Figure 38).
Physical Address Mask 1
48
2-0
Bit
8
7-4
Bits
32
33
Software Environment
34
W
33
C
1
32
U
C
1
31
Physical Base Address 0
Symbol
UC0
WC0
Description
Uncacheable Memory Type
Write-Combining Memory Type
9
AMD-K6™-2E Processor Data Sheet
MTRR0
17
N
O
8
L
2
16
Physical Address Mask 0
7
STEP
4
0
Bits
1
3
2
2
W
C
0
1
BF
0
U
C
0
0
45