AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 210

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
8.6
8.7
192
Cache-Line Replacements
Write Allocate
As programs execute and task switches occur, some cache lines
eventually require replacement.
Instruction cache lines are replaced using a Least Recently
Used (LRU) algorithm. If line replacement is required, lines are
replaced when read cache misses occur.
The data cache uses a slightly different approach to line
replacement. If a miss occurs, and a replacement is required,
lines are replaced by using a Least Recently Allocated (LRA)
algorithm.
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
Write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the data cache. In this case, the
processor performs a 32-byte burst read cycle to fetch the
data-cache line addressed by the pending write cycle. The data
associated with the pending write cycle is merged with the
recently-allocated data-cache line and stored in the processor’s
data cache. The final MESI state of the cache line depends on
the state of the WB/WT# and PWT signals during the burst read
cycle and the subsequent data cache write hit (See Table 34 on
page 198 to determine the cache-line states and the access
types following a cache read miss and cache write hit).
If a data-cache line fetch from memory is attempted because
the write allocate misses the data cache, and KEN# is sampled
In the case of a tag-miss cache fill, the miss is due to a tag
mismatch, in which case the required cache line is filled
from external memory, and the cache line within the sector
that was not required is marked as invalid.
In the case of a tag-hit cache fill, the address matches the
tag, but the requested cache line is marked as invalid. The
required cache line is filled from external memory, and the
cache line within the sector that is not required remains in
the same cache state.
Preliminary Information
Cache Organization
22529B/0—January 2000
Chapter 8