AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 224

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
206
The EWBE control (EWBEC) bits in the EFER register provide
a mechanism for enforcing three different levels of write
ordering in the presence of the write merge buffer:
EFER[3] is defined as the Global EWBE# Disable
(GEWBED). When GEWBED equals 1, the processor does
not attempt to enforce any write ordering internally or
externally (the EWBE# signal is ignored). This is the
maximum performance setting.
EFER[2] is defined as the Speculative EWBE# Disable
(SEWBED). SEWBED only affects the processor when
GEWBED equals 0. If GEWBED equals 0 and SEWBED
equals 1, the processor enforces strong ordering for all
internal write cycles with the exception of write cycles
addressed to a range of memory defined as uncacheable
(UC) or write-combining (WC) by the MTRRs. In addition,
the processor samples the EWBE# signal. If EWBE# is
sampled negated, the processor delays the commitment of
write cycles to processor cache lines in the Modified state or
Exclusive state until EWBE# is sampled asserted.
This setting provides performance comparable to, but
slightly
GEWBED equals 1 because some degree of write ordering is
maintained.
If GEWBED equals 0 and SEWBED equals 0, the processor
enforces strong ordering for all internal and external write
cycles. In this setting, the processor assumes, or speculates,
that strong order must be maintained between writes to the
merge buffer and writes that hit the processor’s cache. Once
the merge buffer is written out to the processor’s bus, the
EWBE# signal is sampled. If EWBE# is sampled negated, the
processor delays the commitment of write cycles to
processor cache lines in the Modified state or Exclusive
state until EWBE# is sampled asserted.
This setting is the default after RESET and provides the
lowest performance of the three settings because full write
ordering is maintained.
Preliminary Information
less
Write Merge Buffer
than,
the
performance
obtained
22529B/0—January 2000
Chapter 9
when