AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 204

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
Instruction Cache Line
Data Cache Line
Notes:
Instruction-cache lines have only two coherency states (valid or invalid) rather than the four MESI coherency states of data-cache lines.
Only two states are needed for the instruction cache because these lines are read-only.
Figure 75. Cache Sector Organization
8.1
186
Address
Address
Tag
Tag
Cache Line 0
Cache Line 1
Cache Line 0
Cache Line 1
MESI States in the Data Cache
Byte 31
Byte 31
Byte 31
Byte 31
The processor cache design takes advantage of a sectored
organization (See Figure 75). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate MESI (modified,
exclusive, shared, invalid) bits that track the state of each cache
line.
The state of each line in the caches is tracked by the MESI bits.
The coherency of these states or MESI bits is maintained by
internal processor snoops and external inquiries by the system
logic. The following four states are defined for the data cache:
Predecode Bits
Predecode Bits
Modified—This line has been modified and is different from
main memory.
Exclusive—This line is not modified and is the same as
external memory. If this line is written to, it becomes
Modified.
Shared—If a cache line is in the Shared state it means that
the same line can exist in more than one cache system.
Invalid—The information in this line is not valid.
Preliminary Information
Byte 30
Byte 30
Cache Organization
Byte 30
Byte 30
Predecode Bits
Predecode Bits
........
........
........
........
........
........
........
........
Byte 0
Byte 0
Predecode Bits
Predecode Bits
Byte 0
Byte 0
22529B/0—January 2000
2 MESI Bits
2 MESI Bits
Chapter 8
1 MESI Bit
1 MESI Bit