AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 220
AMD-K6-2E/400AFR
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AMD-K6™-2E Processor Data Sheet
Table 35. Cache States for Inquire Cycles, Snoops, Flushes, and Invalidation
202
Notes:
All writebacks are 32-byte burst write cycles.
Type of Operation
WBINVD Instruction
INVD Instruction
FLUSH# Signal
Internal Snoop
Inquire Cycle
(F/I = 0)
(F/I = 1)
PFIR
PFIR
Cache State
Before Operation
Shared or exclusive
Modified
Shared or exclusive
Modified
Shared or
exclusive
Modified
Shared or exclusive
Modified
Not applicable or none Not applicable or none
Shared or exclusive
Modified
Not applicable or none Not applicable or none
Preliminary Information
Memory Access
Not applicable or none
Writeback to bus
Not applicable or none
Writeback to bus
Not applicable or none
Writeback to bus
Not applicable or none
Writeback to bus
Not applicable or none
Writeback to bus
Cache Organization
INV=0
INV=1
INV=0
INV=1
MESI State
Cache State After Operation
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Shared
Invalid
Shared
Invalid
Writeback/
Writethrough State
Writethrough
Invalid
Writethrough
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
22529B/0—January 2000
Chapter 8
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