AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 287

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
Figure 89. CLK Waveform
15.4
Valid Delay and Float
Timing
Setup and Hold
Timing
Chapter 15
Valid Delay, Float, Setup, and Hold Timings
The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Likewise, the minimum valid delay timings are used
to analyze hold times to the system logic.
The setup and hold time requirements for the AMD-K6-2E
processor input signals must be met by the system logic to
assure the proper operation of the processor.
0.8 V
Valid delay and float timings are given for output signals
during functional operation and are given relative to the
rising edge of CLK.
During boundary-scan testing, valid delay and float timings
for output signals are with respect to the falling edge of
TCK.
The setup and hold timings during functional and
boundary-scan test mode are given relative to the rising
edge of CLK and TCK, respectively.
1.5 V
2.0 V
Signal Switching Characteristics
t
5
t
2
t
1
t
4
AMD-K6™-2E Processor Data Sheet
t
3
269