AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 164

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
6.4
Basic I/O Read and
Write
Figure 56. Basic I/O Read and Write
146
BE[7:0]#
D[63:0]
A[31:3]
BRDY#
M/IO#
ADS#
W/R#
D/C#
CLK
I/O Read and Write
ADDR
The processor accesses I/O when it executes an I/O instruction
(for example, IN or OUT). Figure 56 shows an I/O read followed
by an I/O write. The processor drives M/IO# Low and D/C# High
during I/O cycles. In this example, the first cycle shows a single
wait state I/O read cycle. It follows the same sequence as a
single-transfer memory read cycle. The processor drives ADS#
to initiate the bus cycle, then it samples BRDY# on every clock
edge starting with the clock edge after the clock edge that
negates ADS#. The system logic must return BRDY# to
complete the cycle. When the processor samples BRDY#
asserted, it can assert ADS# for the next cycle off the next clock
edge. (In this example, an I/O write cycle.)
The I/O write cycle is similar to a memory write cycle, but the
processor drives M/IO# low during an I/O write cycle. The
processor asserts ADS# to initiate the bus cycle. The processor
drives D[63:0] with valid data one clock edge after the clock
edge on which ADS# is asserted. The system logic must assert
BRDY# when the data is properly stored to the I/O destination.
The processor samples BRDY# on every clock edge starting with
the clock edge after the clock edge that negates ADS#. In this
example, two wait states are inserted while the processor waits
for BRDY# to be asserted.
DATA
I/O Read Cycle
Preliminary Information
DATA
Bus Cycles
IDLE
ADDR
DATA
I/O Write Cycle
DATA
22529B/0—January 2000
DATA
Chapter 6
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