AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 166

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
6.5
Hold and Hold
Acknowledge Cycle
148
Inquire and Bus Arbitration Cycles
The AMD-K6-2E processor provides built-in level-one data and
instruction caches. Each cache is 32 Kbytes and two-way
set-associative. The system logic or other bus master devices
can initiate an inquire cycle to maintain cache/memory
coherency. In response to the inquire cycle, the processor
compares the inquire address with its cache tag addresses in
both caches, and, if necessary, updates the MESI state of the
cache line and performs writebacks to memory.
An inquire cycle can be initiated by asserting AHOLD, BOFF#,
or HOLD. AHOLD is exclusively used to support inquire cycles.
During AHOLD-initiated inquire cycles, the processor only
floats the address bus. BOFF# provides the fastest access to the
bus because it aborts any processor cycle that is in-progress,
whereas AHOLD and HOLD both permit an in-progress bus
cycle to complete. During HOLD-initiated and BOFF#-initiated
inquire cycles, the processor floats all of its bus-driving signals.
The system logic or another bus device can assert HOLD to
initiate an inquire cycle or to gain full control of the bus. When
the A MD -K 6-2E p rocess or sam p l es H OL D as sert ed, i t
completes any in-progress bus cycle and asserts HLDA to
acknowledge release of the bus. The processor floats the
following signals off the same clock edge on which HLDA is
asserted:
Figure 58 shows a basic HOLD/HLDA operation. In this
example, the processor samples HOLD asserted during the
memory read cycle. It continues the current memory read cycle
until BRDY# is sampled asserted. The processor drives HLDA
and floats its outputs one clock edge after the last BRDY# of the
cycle is sampled asserted. The system logic can assert HOLD for
as long as it needs to utilize the bus. The processor samples
A[31:3]
ADS#
AP#
BE[7:0]#
CACHE#
D[63:0]
D/C#
Preliminary Information
Bus Cycles
DP[7:0]
LOCK#
M/IO#
PCD
PWT
SCYC
W/R#
22529B/0—January 2000
Chapter 6