AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 128

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
5.30
Pin Attribute
Pin Location
Summary
Sampled
5.31
Pin Attribute
Pin Location
Summary
Sampled
110
INTR (Maskable Interrupt)
INV (Invalidation Request)
Input
AD-34
INTR is the system’s maskable interrupt input to the processor.
When the processor samples and recognizes INTR asserted, the
processor executes a pair of interrupt acknowledge bus cycles
and then jumps to the interrupt service routine specified by the
interrupt number that was returned during the interrupt
acknowledge sequence. The processor only recognizes INTR if
the interrupt flag (IF) in the EFLAGS register equals 1.
The processor samples INTR as a level-sensitive input on every
clock edge, but the interrupt request is not recognized until the
next instruction boundary. The system logic can drive INTR
either synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks. In order to be recognized, INTR must remain
asserted until an interrupt acknowledge sequence is complete.
Input
U-05
During an inquire cycle, the state of INV determines whether
an addressed cache line that is found in the processor’s
instruction or data cache transitions to the invalid state or the
shared state.
If INV is sampled asserted during an inquire cycle, the
processor transitions the cache line (if found) to the invalid
state, regardless of its previous state. If INV is sampled negated
during an inquire cycle, the processor transitions the cache line
(if found) to the shared state. In either case, if the cache line is
found in the modified state, the processor writes it back to
memory before changing its state.
INV is sampled on the clock edge on which EADS# is sampled
asserted.
Preliminary Information
Signal Descriptions
22529B/0—January 2000
Chapter 5