AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 36

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
Figure 5. AMD-K6™-2E Processor Scheduler
2.5
18
Centralized RISC86
Operation Scheduler
Execution Units
®
The AMD-K6-2E processor contains ten parallel execution
units—store, load, integer X ALU, integer Y ALU, MMX ALU
(X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU,
floating-point, and branch condition. Each unit is independent
and capable of handling the RISC86 operations. Table 1 on
page 19 details the execution units, functions performed within
these units, operation latency, and operation throughput.
The store and load execution units are two-stage pipelined
designs.
RISC86 #0
The store unit performs data writes and register calculation
for LEA/PUSH. Data memory and register writes from stores
are available after one clock. Store operations are held in a
store queue prior to execution. From there, they execute in
order.
The load unit performs data memory reads. Data is available
from the load unit after two clocks.
Preliminary Information
RISC86 #1
Internal Architecture
RISC86 Operation Buffer
From Decode Logic
RISC86 #2
RISC86 #3
RISC86 Issue Buses
22529B/0—January 2000
Chapter 2