AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 221

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
Cache Snooping
Table 36. Snoop Action
Notes:
1. The processor’s response to an inquire cycle depends on the state of the INV input signal and the state of the cache line as
2. If an internal snoop hits a modified line in the data cache, the line is written back and invalidated. Then the instruction cache
3. If an internal snoop hits a line in the instruction cache, the instruction cache line is invalidated and the data-cache read or write
Chapter 8
follows:
For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but if INV is sampled asserted, the line is
invalidated.
For the data cache, if INV is sampled negated, valid lines remain in or transition to the Shared state, a modified data cache line
is written back before the line is marked shared (with HITM# asserted), and invalid lines remain invalid. For the data cache, if
INV is sampled asserted, the line is marked invalid. Modified lines are written back before invalidation.
performs a burst read from memory.
is performed from memory.
Type of Event
Internal Snoop
Inquire Cycle
Instruction Cache
Table 36 shows the conditions under which snooping occurs in
the AMD-K6-2E processor and the resources that are snooped.
Data Cache
Type of Access
System Logic
Cache Organization
Write
Write
Read
Read
Read
Read
Miss
Miss
Miss
Hit
Hit
Hit
Instruction Cache
Not applicable
Not applicable
Yes
Yes
Yes
No
No
1
3
3
AMD-K6™-2E Processor Data Sheet
Snooping Action
Not applicable
Not applicable
Not applicable
Not applicable
Data Cache
Yes
Yes
No
1
2
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