HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 111

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.8
5.8.1
The SP value must always be a multiple of 4. If it is not, an address error will occur when the
stack is accessed during exception handling.
5.8.2
The VBR value must always be a multiple of 4. If it is not, an address error will occur when the
stack is accessed during exception handling.
5.8.3
When the SP value is not a multiple of 4, an address error will occur when stacking for exception
handling (interrupts, etc.) and address error exception handling will start after the first exception
handling is ended. Address errors will also occur in the stacking for this address error exception
handling. To ensure that address error exception handling does not go into an endless loop, no
address errors are accepted at that point. This allows program control to be passed to the handling
routine for address error exception and enables error processing.
When an address error occurs during exception handling stacking, the stacking bus cycle (write) is
executed. When stacking the SR and PC values, the SP values for both are subtracted by 4,
therefore, the SP value is still not a multiple of 4 after the stacking. The address value output
during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is
undefined.
5.8.4
Some specifications on slot illegal instruction exception handling in this LSI differ from those on
the conventional SH2.
• Conventional SH2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot
• This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal
The supporting status on our software products regarding this note is as follows:
illegal instructions.
instructions.
Usage Notes
Value of Stack Pointer (SP)
Value of Vector Base Register (VBR)
Address Errors Caused by Stacking for Address Error Exception Handling
Notes on Slot Illegal Instruction Exception Handling
Rev. 6.00 Jun. 12, 2007 Page 79 of 610
Section 5 Exception Handling
REJ09B0131-0600