HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 446

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface (HIF)
When the external DMAC is specified to detect high level of the HIFDREQ signal, set DMD = 0
and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after writing 1
to the DTRG bit, HIFDREQ remains high until low level is detected for both the HIFCS and
HIFRS signals.
In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to
HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If t
stipulated in section 21.4.9, HIF Timing, are not satisfied, the HIFDREQ signal may be negated
unintentionally.
When the external DMAC is specified to detect the falling edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 0. After writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is
generated at the HIFDREQ pin.
Rev. 6.00 Jun. 12, 2007 Page 414 of 610
REJ09B0131-0600
HIFDREQ
HIFDREQ
DTRG bit
DTRG bit
DPOL bit
DPOL bit
HIFCS
HIFRS
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
Figure 15.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0)
Figure 15.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
Negated when HIFCS = HIFRS = low level.
Latency is t
After assert, negated when
t
PCYC
(peripheral clock cycle) × 32 cyc have elapsed.
PCYC
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
(peripheral clock cycle) × 3 cyc or less.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
HIFAS
and t
HIFAH