HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 411

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In transmitting serial data, the SCIF operates as follows:
1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
3. The SCIF checks the SCFTDR transmit data at the timing for sending the MSB (bit 7). If data
4. After the end of serial transmission, the SCK pin is held in the high state.
Figure 14.14 shows an example of SCIF transmit operation.
data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that
the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to
SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting).
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the
FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register
(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is
generated.
If clock output mode is selected, the SCIF outputs eight synchronous clock pulses. If an
external clock source is selected, the SCIF outputs data in synchronization with the input
clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
is present, the data is transferred from SCFTDR to SCTSR, the MSB (bit 7) is sent, and then
serial transmission of the next frame is started. If there is no transmit data, the TEND flag in
SCFSR is set to 1, the MSB (bit 7) is sent, and then the TxD pin holds the states.
Synchronization
Serial data
TEND
TDFE
clock
interrupt
request
Figure 14.14 Example of SCIF Transmit Operation
TXI
Data written to SCFTDR
Bit 0
LSB
and TDFE flag cleared
to 0 by TXI interrupt
handler
Bit 1
One frame
Section 14 Serial Communication Interface with FIFO (SCIF)
interrupt
request
MSB
Bit 7
TXI
Bit 0
Rev. 6.00 Jun. 12, 2007 Page 379 of 610
Bit 1
Bit 6
Bit 7
REJ09B0131-0600