HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 388
HD6417618
Manufacturer Part Number
HD6417618
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417618.pdf
(646 pages)
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Section 14 Serial Communication Interface with FIFO (SCIF)
14.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the number of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the number of
transmit data in SCFTDR with the upper eight bits, and the number of receive data in SCFRDR
with the lower eight bits. SCFDR can always be read from by the CPU. SCFDR is initialized to
H'0000 by a power on reset.
Rev. 6.00 Jun. 12, 2007 Page 356 of 610
REJ09B0131-0600
Bit
15 to 13
12
11
10
9
8
7 to 5
4
3
2
1
0
Bit Name
T4
T3
T2
T1
T0
R4
R3
R2
R1
R0
Initial
value
All 0
0
0
0
0
0
All 0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicate the number of non-transmitted data stored in
SCFTDR. H'00 means no transmit data, and H'10
means that SCFTDR is full of transmit data.
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicate the number of receive data stored in SCFRDR.
H'00 means no receive data, and H'10 means that
SCFRDR full of receive data.
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