HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 307

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.2.9
RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not
transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive
frames in the FIFO are discarded. The number of frames discarded at this time is counted. When
the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the
counter value is cleared to 0. Write operations to this register have no effect.
12.2.10 Transmit FIFO Threshold Register (TFTR)
TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the
first transmission is started. The actual threshold is 4 times the set value. The EtherC starts
transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified
by this register, when the transmit FIFO is full, or when 1-frame write is executed. When setting
this register, do so in the transmission-halt state.
Bit
31 to 16
15 to 0
Bit
31 to 11
Receive Missed-Frame Counter Register (RMFCR)
Bit Name

MFC15 to
MFC0
Bit Name

Initial
value
All 0
All 0
Initial
value
All 0
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R
R
R
R/W
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
Missed-Frame Counter
Indicate the number of frames that are discarded and
not transferred to the receive buffer during reception.
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
Description
Rev. 6.00 Jun. 12, 2007 Page 275 of 610
REJ09B0131-0600