HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 510

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18 User Break Controller (UBC)
Rev. 6.00 Jun. 12, 2007 Page 478 of 610
REJ09B0131-0600
Bit
7
6
5
4
3
2
1
0
Bit Name
CDB1
CDB0
IDB1
IDB0
RWB1
RWB0
SZB1
SZB0
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
L Bus Cycle/I Bus Cycle Select B
Select the L bus cycle or I bus cycle as the bus cycle of the
channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Instruction Fetch/Data Access Select B
Select the instruction fetch cycle or data access cycle as
the bus cycle of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
Read/Write Select B
Select the read cycle or write cycle as the bus cycle of the
channel B break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
Operand Size Select B
Select the operand size of the bus cycle for the channel B
break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
data access cycle