HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 18

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I/O Ports............................................................................................. 457
17.1 Port A................................................................................................................................. 457
17.2 Port B ................................................................................................................................. 459
17.3 Port C ................................................................................................................................. 461
17.4 Port D................................................................................................................................. 464
17.5 Port E ................................................................................................................................. 466
17.6 Usage Note......................................................................................................................... 469
Section 18 User Break Controller (UBC)............................................................ 471
18.1 Features.............................................................................................................................. 471
18.2 Register Descriptions......................................................................................................... 473
Rev. 6.00 Jun. 12, 2007 Page xviii of xxxii
16.1.3 Port B IO Register L (PBIORL) ........................................................................... 436
16.1.4 Port B Control Register L1 and L2 (PBCRL1 and PBCRL2)............................... 436
16.1.5 Port C IO Register H and L (PCIORH and PCIORL) .......................................... 440
16.1.6 Port C Control Register H2, L1, and L2 (PCCRH2, PCCRL1, and PCCRL2)..... 440
16.1.7 Port D IO Register L (PDIORL)........................................................................... 445
16.1.8 Port D Control Register L2 (PDCRL2) ................................................................ 446
16.1.9 Port E IO Register H and L (PEIORH and PEIORL) ........................................... 448
16.1.10 Port E Control Register H1, H2, L1, and L2 (PECRH1, PECRH2, PECRL1, and
17.1.1 Register Description ............................................................................................. 457
17.1.2 Port A Data Register H (PADRH) ........................................................................ 457
17.2.1 Register Description ............................................................................................. 459
17.2.2 Port B Data Register L (PBDRL) ......................................................................... 459
17.3.1 Register Description ............................................................................................. 462
17.3.2 Port C Data Registers H and L (PCDRH and PCDRL) ........................................ 462
17.4.1 Register Description ............................................................................................. 464
17.4.2 Port D Data Register L (PDDRL)......................................................................... 464
17.5.1 Register Description ............................................................................................. 467
17.5.2 Port E Data Registers H and L (PEDRH and PEDRL) ......................................... 467
18.2.1 Break Address Register A (BARA)...................................................................... 473
18.2.2 Break Address Mask Register A (BAMRA)......................................................... 474
18.2.3 Break Bus Cycle Register A (BBRA)................................................................... 474
18.2.4 Break Address Register B (BARB) ...................................................................... 475
18.2.5 Break Address Mask Register B (BAMRB) ......................................................... 476
18.2.6 Break Data Register B (BDRB)............................................................................ 476
18.2.7 Break Data Mask Register B (BDMRB)............................................................... 477
18.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 477
18.2.9 Break Control Register (BRCR) ........................................................................... 479
PECRL2) .............................................................................................................. 448