HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 207

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 7.23 shows the auto-refreshing cycle timing. After starting the auto-refreshing, PALL
command is issued in the Tp cycle to make all the banks to precharged state from active state
when some bank is being precharged. Then the REF command is issued in the Trr cycle after
inserting idle cycles of which number is specified by bits WTRP1 and WTRP0 in CSnWCR. A
new command is not issued for the duration of the number of cycles specified by bits WTRC1
and WTRC0 in CSnWCR after the Trr cycle. Bits WTRC1 and WTRC0 in CSnWCR must be
set so as to satisfy the SDRAM refreshing cycle time (tRC). A Tpw cycle is inserted between
the Tp cycle and Trr cycle when the setting of bits WTRP1 and WTRP0 in CSnWCR is longer
than or equal to one cycle.
D15 to D0
A25 to A0
Note: * Address pin to be connected to pin A10 of SDRAM.
RD/WR
DQMxx
CKIO
A11*
RAS
CAS
CSn
BS
Figure 7.23 Auto-Refreshing Timing
Tp
Tpw
Trr
Hi-z
Trc
Rev. 6.00 Jun. 12, 2007 Page 175 of 610
Trc
Section 7 Bus State Controller (BSC)
Trc
REJ09B0131-0600