HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 438

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface (HIF)
15.4.10 HIFDREQ Trigger Register (HIFDTR)
HIFDTR is a 32-bit register. Writing to HIFDTR by the on-chip CPU asserts the HIFDREQ pin.
HIFDTR cannot be accessed by an external device.
Rev. 6.00 Jun. 12, 2007 Page 406 of 610
REJ09B0131-0600
Bit
0
Bit
31 to 1
Bit Name
Bit Name
—
AC
Initial
Value
0/1
Initial
Value
All 0
R/W
R/W
R/W
R*
1
Description
HIFRAM Access Exclusive Control
Controls accessing of HIFRAM by the on-chip CPU for
the HIFRAM bank selected by the BMD and BSEL bits
in HIFSCR as the bank allowed to be accessed by this
LSI.
0: The on-chip CPU can perform reading/writing of
1: When an HIFRAM read/write operation by the on-
When booted in non-HIF boot mode, the initial value of
this bit is 0.
When booted in HIF boot mode, the initial value of this
bit is 1. After an external device writes a boot program
to HIFRAM via the HIF, clearing this bit to 0 boots the
on-chip CPU from HIFRAM.
When 1 is written to this bit by an external device, H'A5
should be written to bits 7 to 0 to prevent erroneous
writing.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
HIFRAM.
chip CPU occurs, the CPU enters the wait state, and
execution of the instruction is halted until this bit is
cleared to 0.