HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 445

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

15.8
Figures 15.8 to 15.11 show the HIFDREQ output timing. The start of the HIFDREQ assert
synchronizes with the DTRG bit in HIFDTR being set to 1. The HIFDREQ negate timing and
assert level are determined by the DMD and DPOL bits in HIFSCR, respectively.
When the external DMAC is specified to detect low level of the HIFDREQ signal, set DMD = 0
and DPOL = 0. After writing 1 to the DTRG bit, the HIFDREQ signal remains low until low level
is detected for both the HIFCS and HIFRS signals.
In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to
HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If t
stipulated in section 21.4.9, HIF Timing, are not satisfied, the HIFDREQ signal may be negated
unintentionally.
HIFDREQ
DTRG bit
DPOL bit
HIFD15 to HIFD00
HIFCS
HIFRS
External DMAC Interface
HIFWR
HIFRD
HIFCS
HIFRS
Figure 15.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)
Asserted in synchronization with the
DTRG bit being set by the on-chip CPU.
Figure 15.7 Consecutive Data Reading from HIFRAM
HIFADR setting
[15:8] = AH
[7:0] = AL
0016 AHAL 000A
HIFMCR setting
Consecutive read
Auto-increment
Negated when HIFCS = HIFRS = low level.
Latency is t
0088
PCYC
0018 D0D1 D2D3 D4D5 D6D7 D8D9
HIFDATA
selection
(peripheral clock cycle) × 3 cyc or less.
Rev. 6.00 Jun. 12, 2007 Page 413 of 610
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
Consecutive data reading
Section 15 Host Interface (HIF)
DADB
REJ09B0131-0600
HIFAS
DCDD
and t
HIFAH