HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 27

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 21.37 SCK Input Clock Timing....................................................................................... 580
Figure 21.38 SCI Input/Output Timing in Clocked Synchronous Mode .................................... 581
Figure 21.39 I/O Port Timing ..................................................................................................... 581
Figure 21.40 HIF Access Timing ............................................................................................... 583
Figure 21.41 HIFINT and HIFDREQ Timing ............................................................................ 583
Figure 21.42 HIFRDY and HIF Pin Enable/Disable Timing...................................................... 584
Figure 21.43 MII Transmission Timing (Normal Operation)..................................................... 586
Figure 21.44 MII Transmission Timing (Collision Occurred).................................................... 586
Figure 21.45 MII Reception Timing (Normal Operation) .......................................................... 587
Figure 21.46 MII Reception Timing (Error Occurred) ............................................................... 587
Figure 21.47 MDIO Input Timing .............................................................................................. 587
Figure 21.48 MDIO Output Timing ........................................................................................... 587
Figure 21.49 WOL Output Timing ............................................................................................. 588
Figure 21.50 EXOUT Output Timing......................................................................................... 588
Figure 21.51 TCK Input Timing................................................................................................. 589
Figure 21.52 TCK Input Timing in Reset Hold State ................................................................. 589
Figure 21.53 H-UDI Data Transmission Timing ........................................................................ 589
Figure 21.54 Output Load Circuit............................................................................................... 590
Figure 21.55 Load Capacitance versus Delay Time ................................................................... 591
Appendix
Figure C.1 Package Dimensions (BP-176) ................................................................................. 598
Rev. 6.00 Jun. 12, 2007 Page xxvii of xxxii