HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 447

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

When the external DMAC is specified to detect the rising edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after
writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is generated at the HIFDREQ
pin.
When the external DMAC supports intermittent operating mode (block transfer mode), efficient
data transfer can be implemented by using the HIFRAM consecutive access and bank functions.
HIFDREQ
DTRG bit
DPOL bit
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
Figure 15.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1)
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
After assert, negated when
t
PCYC
(peripheral clock cycle) × 32 cyc have elapsed.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
Rev. 6.00 Jun. 12, 2007 Page 415 of 610
Section 15 Host Interface (HIF)
REJ09B0131-0600