HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 514

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18 User Break Controller (UBC)
18.2.10 Execution Times Break Register (BETR)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2
decremented by 1. A break is issued when the break condition is satisfied after BETR becomes
H'0001.
18.2.11 Branch Source Register (BRSR)
BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source
instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0
when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on
reset. Other bits are not initialized by a power-on reset. The four BRSR registers have a queue
structure and a stored register is shifted at every branch.
Rev. 6.00 Jun. 12, 2007 Page 482 of 610
REJ09B0131-0600
Bit
15 to 12
11 to 0
Bit
31
Bit Name
SVF
Bit Name
—
BET11 to
BET0
12
Initial
Value
0
Initial
Value
All 0
All 0
– 1 times. Every time the break condition is satisfied, BETR is
R/W
R
R/W
R/W
R
Description
These bits are always read as 0. The write value should
always be 0.
Reserved
Number of Execution Times
Description
BRSR Valid Flag
Indicates whether or not the branch source address is
stored. When a branch is made, this flag is set to 1.
This flag is cleared to 0 by one of the following
conditions: when this flag is read from this register,
when PC trace is enabled, and when a power-on
reset is generated.
0: The value of BRSR register is invalid
1: The value of BRSR register is valid