HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 54

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
• Global-base register (GBR)
• Vector-base register (VBR)
2.2.3
There are four 32-bit system registers, designated two multiply and accumulate registers (MACH
and MACL), a procedure register (PR), and program counter (PC).
• Multiply and accumulate registers (MAC)
• Procedure register (PR)
• Program counter (PC)
Rev. 6.00 Jun. 12, 2007 Page 22 of 610
REJ09B0131-0600
Bit
0
This register indicates a base address in GBR indirect addressing mode. The GBR indirect
addressing mode is used for data transfer of the on-chip peripheral module registers and logic
operations.
This register indicates the base address of the exception handling vector table.
This register stores the results of multiplication and multiply-and-accumulate operation.
This register stores the return-destination address from subroutine procedures.
The PC indicates the point which is four bytes (two instructions) after the current execution
instruction.
System Registers
Bit
name
T
Default
Undefined
Read/
Write
R/W
Description
Indicates true (1) or false (0) in the following
instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S),
BF (BF/S), SETT, CLRT
Indicates carry, borrow, overflow, or underflow in the
following instructions: ADDV, ADDC, SUBV, SUBC,
NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR,
SHLL, ROTR, ROTL, ROTCR, ROTCL
T