HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 335

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HD6417618

Manufacturer Part Number
HD6417618
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Manufacturer:
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1.
2.
3.
4.
5.
7.
TC: EESR frame transmission complete
Figure 12.9 Countermeasure by Monitoring the Transmit Descriptor in Processing of
: Processing added as the countermeasure for the problem
After setting the transmit
descriptor, set the TR bit in EDTRR to 1.
After setting the corresponding transmit
descriptor, set the TR bit in EDTRR to 1.
Prepare the condition flag and turn it off.
Prepare multiple transmit descriptors.
Read the TACT bit of the
corresponding transmit descriptor.
Transmission task
Transmission starts
Next transmission task
generated?
Interrupts Other than the Frame Transmit Complete (TC) Interrupt
TACT = 0?
Yes
Yes
No
No
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
5.
6.
Make an OS service call to place
the transmission task in a waiting state.
been brought out of the waiting state
End
Turn the condition flag on.
Has the transmission task
by the interrupt handler?
Yes
Rev. 6.00 Jun. 12, 2007 Page 303 of 610
No
Make an OS service call to bring the
transmission task out of the waiting state.
Make an OS service call to bring the
transmission task out of the waiting state.
Read the TACT bit of the corresponding
transmit descriptor.
Generation of EtherC/E-DMAC
interrupt
Interrupt processing for interrupts
other than TC
Save EESR and clear the bit
by writing a 1.
Turn off the condition flag.
Interrupt other than TC?
Is the condition flag on?
Interrupt handler
TC interrupt?
TACT = 0?
End
Yes
Yes
Yes
Yes
REJ09B0131-0600
No
No
No
No

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