HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 284

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Ethernet Controller (EtherC)
11.4.4
MII registers in the PHY are accessed via this LSI’s PHY interface register (PIR). Connection is
made as a serial interface in accordance with the MII frame format specified in IEEE802.3u.
MII Management Frame Format: The format of an MII management frame is shown in figure
11.8. To access an MII register, a management frame is implemented by the program in
accordance with the procedures shown in MII Register Access Procedure.
Rev. 6.00 Jun. 12, 2007 Page 252 of 610
REJ09B0131-0600
[Legend]
PRE:
ST:
OP:
PHYAD:
REGAD:
TA:
DATA:
IDLE:
Access Type
Item
Number of bits
Read
Write
Accessing MII Registers
32 consecutive 1s
Write of 01 indicating start of frame
Write of code indicating access type
Write of 0001 if the PHY address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY address.
Write of 0001 if the register address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY register address.
Time for switching data transmission source on MII interface
(a) Write: 10 written
(b) Read: Bus release (notation: Z0) performed
16-bit data. Sequential write or read from MSB
(a) Write: 16-bit data write
(b) Read: 16-bit data read
Wait time until next MII management format input
(a) Write: Independent bus release (notation: X) performed
(b) Read: Bus already released in TA; control unnecessary
PRE
1..1
1..1
32
Figure 11.5 MII Management Frame Format
ST
01
01
2
OP
10
01
2
MII Management Frame
PHYAD
00001
00001
5
RRRRR
RRRRR
REGAD
5
TA
Z0
10
2
DATA
D..D
D..D
16
IDLE
X