MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 160

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Power Management
6.4.4 JTAG
6.4.5 Interrupt Controller
6.4.6 Edge Port
6.4.7 Random-Access Memory (RAM)
Advance Information
160
The JTAG (Joint Test Action Group) controller logic is clocked using the
TCLK input and is not affected by the system clock. The JTAG cannot
generate an event to cause the CPU to exit any low-power mode.
Toggling TCLK during any low-power mode will increase the system
current consumption.
The interrupt controller is not affected by any of the low-power modes.
All logic between the input sources and generating the interrupt to the
M•CORE processor will be combinational to allow the ability to wakeup
the CPU processor during low-power stop mode when all system clocks
are stopped.
A fast interrupt request will cause the CPU to exit a low-power mode only
if the FE bit in the CPU’s PSR register is set. A normal interrupt request
will cause the CPU to exit a low-power mode only if the IE and EE bits in
the CPU’s PSR register are set.
In wait and doze modes, the edge port continues to operate normally and
may be configured to generate interrupts (either an edge transition or
low level on an external pin) to exit the low-power modes.
In stop mode, there are no clocks available to perform the edge detect
function. Thus, only the level detect logic is active (if configured) to allow
any low level on the external interrupt pin to generate an interrupt (if
enabled) to exit the stop mode.
The random-access memory (RAM) is disabled during any low-power
mode. No recovery time is required when exiting any low-power mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Power Management
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA