MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 324

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Modules (TIM1 and TIM2)
16.7.1 Timer Input Capture/Output Compare Select Register
Advance Information
324
0x00ce_0017
0x00ce_0018
0x00ce_0019
0x00ce_001a
0x00ce_001b
0x00ce_001d
0x00ce_001e
1. S = CPU supervisor mode access only.
2. Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
0x00ce_001c
0x00ce_001f
TIM1
Address
0x00cf_0017
0x00cf_0018
0x00cf_0019
0x00cf_001a
0x00cf_001b
0x00cf_001c
0x00cf_001d
0x00cf_001e
0x00cf_001f
TIM2
Table 16-2. Timer Modules Memory Map (Continued)
Address: TIM1 — 0x00ce_0000
Reset:
Read: Anytime; always read $00
Write: Anytime
IOS[3:0] — I/O Select Bits
Read:
Write:
The IOS[3:0] bits enable input capture or output compare operation
for the corresponding timer channels.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Output compare enabled
0 = Input capture enabled
TIM2 — 0x00cf_0000
Figure 16-2. Timer Input Capture/Output Compare
Bit 7
0
0
Pulse Accumulator Counter Register High (TIMPACNTH)
Pulse Accumulator Counter Register Low (TIMPACNTL)
Timer Modules (TIM1 and TIM2)
Pulse Accumulator Control Register (TIMPACTL)
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Pulse Accumulator Flag Register (TIMPAFLG)
Timer Port Data Direction Register (TIMDDR)
= Writes have no effect and the access terminates without a transfer error exception.
Timer Channel 3 Register Low (TIMC3L)
6
0
0
Timer Port Data Register (TIMPORT)
Timer Test Register (TIMTST)
Select Register (TIMIOS)
5
0
0
Reserved
Bits 7–0
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
4
0
0
(2)
IOS3
3
0
IOS2
2
0
IOS1
1
0
MOTOROLA
Access
²
IOS0
S
S
S
S
S
S
S
Bit 0
S
0
(1)