MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 192

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Interrupt Controller Module
8.8.1 Interrupt Sources and Prioritization
8.8.2 Fast and Normal Interrupt Requests
Advance Information
192
Each interrupt source in the system sends a unique signal to the interrupt
controller. Up to 40 interrupt sources are supported. Each interrupt
source can be programmed to one of 32 priority levels by programing the
PLS bits of the PLSR in the interrupt controller. The highest priority level
is 31 and lowest priority level is 0. By default, each interrupt source is
assigned to the priority level 0. Each interrupt source is associated with
a 5-bit priority level select value that selects one of 32 priority levels. The
interrupt controller uses the priority levels as the basis for the generation
of all interrupt signals to the CPU.
Interrupt requests may be forced by software by writing to IFRH and
IFRL. Each bit of IFRH and IFRL is logically ORed with the
corresponding interrupt source signal before the priority level select
logic. To negate the forced interrupt request, the interrupt handler can
clear the appropriate IFR bit. IPR reflects the state of each priority level.
FIER allows individual enabling or masking of pending fast interrupt
requests. FIER is logically ANDed with IPR, and the result is stored in
FIPR. FIPR bits are bit-wise ORed together and inverted to form the fast
interrupt signal routed to the CPU (see
software to quickly determine the highest priority pending fast interrupt.
The output of FIPR also feeds into a 32-to-5 priority encoder to generate
the vector number to present to the CPU if vectored interrupts are
required.
NIER allows individual enabling or masking of pending normal interrupt
requests. NIER is logically ANDed with IPR, and the result is stored in
NIPR. NIPR bits are bit-wise ORed together and inverted to form the
normal interrupt signal routed to the CPU. The normal interrupt signal is
only asserted if the fast interrupt signal is negated. The NIPR allows
software to quickly determine the highest priority pending normal
interrupt. The output of NIPR also feeds into a 32-to-5 priority encoder to
generate the vector number to present to the CPU if vectored interrupts
are required. If the fast interrupt signal is asserted, then the vector
number is determined by the highest priority fast interrupt.
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Interrupt Controller Module
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Figure
8-1). The FIPR allows
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