MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 231

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

10.8.3 Program and Erase Operations
10.8.3.1 Setting the SGFMCLKD Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Read and write operations are both used for the program and erase
algorithms described in this subsection. These algorithms are controlled
by a state machine whose timebase is derived from the SGFM module
clock via a programmable counter.
The command register and associated address and data buffers operate
as a two stage FIFO so that a new command along with the necessary
address and data can be stored while the previous command is still in
progress. This pipelining speeds when programming more than one
word on a specific row, as the charge pumps can be kept on in between
two programming commands, thus saving the overhead needed to setup
the charge pumps. Buffer empty and command completion are indicated
by flags in the SGFM User Status Register. Interrupts will be requested
if enabled.
Prior to issuing any program or erase commands, SGFMCLKD must be
written to set the FLASH state machine clock (FCLK). The SGFM
module runs at the system clock frequency, but FCLK must be divided
down from the system clock to a frequency between 150 kHz and
200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0]
bits in SGFMCLKD:
1. If f
2. Determine DIV[5:0] by using the following equation. Keep only the
3. Thus the FLASH state machine clock will be:
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
PRDIV8 = 0.
integer portion of the result and discard any fraction. Do not round
the result.
SYS
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is greater than 12.8 MHz, PRDIV8 = 1, otherwise
DIV[5:0] =
FCLK =
Second Generation FLASH for M•CORE (SGFM)
1 + (PRDIV8 x 7)
1 + (PRDIV8 x 7)
DIV[5:0] + 1
200 kHz
f
SYS
f
SYS
Advance Information
SGFM User Mode
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