MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 430

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Queued Analog-to-Digital Converter (QADC)
19.5 Modes of Operation
19.5.1 Debug Mode
Advance Information
430
This subsection describes the two modes of operation in which the
QADC does not perform conversions in a regular fashion:
The QDBG bit in the Module Configuration Register (QADCMCR)
governs behavior of the QADC when the CPU enters background debug
mode. When QDBG is clear, the QADC operates normally and is
unaffected by CPU background debug mode. See
Configuration Register
When QDBG is set and the CPU enters background debug mode, the
QADC finishes any conversion in progress and then freezes. This is
QADC debug mode. Depending on when debug mode is entered, the
three possible queue freeze scenarios are:
When the QADC enters debug mode while a queue is active, the current
CCW location of the queue pointer is saved.
Debug mode:
•
•
•
•
•
•
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Debug mode
Stop mode
When a queue is not executing, the QADC freezes immediately.
When a queue is executing, the QADC completes the current
conversion and then freezes.
If during the execution of the current conversion, the queue
operating mode for the active queue is changed, or a queue 2
abort occurs, the QADC freezes immediately.
Stops the analog clock
Holds the periodic/interval timer in reset
Prevents external trigger events from being captured
Keeps all QADC registers and RAM accessible
Go to: www.freescale.com
(QADCMCR).
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
19.8.1 QADC Module
MOTOROLA