MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 555

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
WS[2:0] — Wait States Field
TAEN — Transfer Acknowledge Enable Bit
The WS field determines the number of wait states for the chip select
logic to insert before asserting the internal cycle termination signal.
One wait state is equal to one system clock cycle. If WS is configured
for zero wait states, then the internal cycle termination signal is
asserted in the clock cycle following the start of the cycle access,
resulting in one-clock transfers. A WS configured for one wait state
means that the internal cycle termination signal is asserted two clock
cycles after the start of the cycle access.
Since the internal cycle termination signal is asserted internally after
the programmed number of wait states, software can adjust the bus
timing to accommodate the access speed of the external device. With
up to seven possible wait states, even slow devices can be interfaced
with the MCU.
The TAEN bit determines whether the internal cycle termination
signal is asserted by the chip select logic when accesses occur to the
address range defined by the corresponding chip select. When TAEN
is 0, an external device is responsible for asserting the external TA pin
to terminate the bus access. When TAEN is 1, the chip select logic
asserts the internal cycle termination signal after a time determined
by the programmed number of wait states. When TAEN is 1, external
Freescale Semiconductor, Inc.
WS[2:0]
For More Information On This Product,
000
001
010
011
100
101
110
111
Table 21-3. Chip Select Wait States Encoding
Go to: www.freescale.com
Read Access
Chip Select Module
0
1
2
3
4
5
6
7
WWS = 0
Write Access
Number of Wait States
0
1
2
3
4
5
6
7
Read Access
0
1
2
3
4
5
6
7
Memory Map and Registers
WWS = 1
Advance Information
Chip Select Module
Write Access
1
2
3
4
5
6
7
8
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