MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 268
MMC2114
Manufacturer Part Number
MMC2114
Description
M CORE Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MMC2114.pdf
(654 pages)
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Clock Module
11.8.6.1 Phase and Frequency Detector (PFD)
11.8.6.2 Charge Pump/Loop Filter
Advance Information
268
The PFD is a dual-latch phase-frequency detector. It compares both the
phase and frequency of the reference and feedback clocks. The
reference clock comes from either the crystal oscillator or an external
clock source. The feedback clock comes from:
When the frequency of the feedback clock equals the frequency of the
reference clock, the PLL is frequency-locked. If the falling edge of the
feedback clock lags the falling edge of the reference clock, the PFD
pulses the UP signal. If the falling edge of the feedback clock leads the
falling edge of the reference clock, the PFD pulses the DOWN signal.
The width of these pulses relative to the reference clock depends on how
much the two clocks lead or lag each other. Once phase lock is
achieved, the PFD continues to pulse the UP and DOWN signals for very
short durations during each reference clock cycle. These short pulses
continually update the PLL and prevent the frequency drift phenomenon
known as dead-banding.
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode
the current magnitude of the charge pump varies with the MFD as shown
in
Table
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
CLKOUT in 1:1 PLL mode, or
VCO output divided by two if CLKOUT is disabled in 1:1 PLL
mode, or
VCO output divided by the MFD in normal PLL mode
11-9.
Charge Pump Current
Go to: www.freescale.com
Table 11-9. Charge Pump Current and MFD
Clock Module
1X
2X
4X
in Normal Mode Operation
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
0
2
6
MFD
MFD < 2
MFD < 6
MFD
MOTOROLA
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