MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 308

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Programmable Interrupt Timer Modules (PIT1 and PIT2)
15.6 Memory Map and Registers
15.6.1 Memory Map
15.6.2 Registers
Advance Information
308
0x00c8_0000
0x00c8_0002
0x00c8_0004
0x00c8_0006
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
Address
only addresses have no effect and result in a cycle termination transfer error.
PIT1
Table 15-1. Programmable Interrupt Timer Modules Memory Map
0x00c9_0000
0x00c9_0002
0x00c9_0004
0x00c9_0006
Address
PIT2
This subsection describes the memory map and register structure for
PIT1 and PIT2.
Refer to
This device has two programmable interrupt timers. PIT1 has a base
address located at 0x00c8_0000. PIT2 base address is 0x00c9_0000.
The PIT programming model consists of these registers:
Programmable Interrupt Timer Modules (PIT1 and PIT2)
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
The PIT Control and Status Register (PCSR) configures the
timer’s operation. See
The PIT Modulus Register (PMR) determines the timer modulus
reload value. See
The PIT Count Register (PCNTR) provides visibility to the counter
value. See
Table 15-1
Go to: www.freescale.com
PIT Control and Status Register (PCSR)
Bits 15–8
15.6.2.3 PIT Count
for a description of the memory map.
PIT Count Register (PCNTR)
PIT Modulus Register (PMR)
15.6.2.2 PIT Modulus
Unimplemented
15.6.2.1 PIT Control and Status
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Register.
(2)
Bits 7–0
Register.
MOTOROLA
Register.
Access
S/U
—
S
S
(1)