MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 37

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Figure
19-40 CCW Freeze Situation 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . .491
19-41 CCW Freeze Situation 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . .491
19-42 QADC Clock Subsystem Functions . . . . . . . . . . . . . . . . . . . . 503
19-43 QADC Conversion Queue Operation . . . . . . . . . . . . . . . . . . . 506
19-44 Equivalent Analog Input Circuitry . . . . . . . . . . . . . . . . . . . . . . 510
19-45 Errors Resulting from Clipping . . . . . . . . . . . . . . . . . . . . . . . . 511
19-46 External Positive Edge Trigger Mode Timing with Pause. . . . 512
19-47 Gated Mode, Single Scan Timing . . . . . . . . . . . . . . . . . . . . . . 514
19-48 Gated Mode, Continuous Scan Timing. . . . . . . . . . . . . . . . . . 514
19-49 Star-Ground at the Point of Power Supply Origin . . . . . . . . . . 516
19-50 Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . . . . 518
19-51 Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . . . .518
19-52 External Multiplexing of Analog Signal Sources . . . . . . . . . . . 520
19-53 Electrical Model of an A/D Input Pin . . . . . . . . . . . . . . . . . . . . 521
20-1 Read Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
20-2 Write Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
20-3 Master Mode — 1-Clock Read and Write Cycle . . . . . . . . . . . 539
20-4 Master Mode — 2-Clock Read and Write Cycle . . . . . . . . . . . 539
20-5 Internal (Show) Cycle Followed by External 1-Clock Read . . 542
20-6 Internal (Show) Cycle Followed by External 1-Clock Write . . 543
21-1 Chip Select Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
21-2 Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . . . . 551
21-3 Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . . . . 552
21-4 Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . . . . 552
21-5 Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . . . . 553
22-1 Top-Level Tap Module and Low-Level (OnCE)
22-2 Top-Level TAP Controller State Machine . . . . . . . . . . . . . . . . 566
22-3 IDCODE Register Bit Specification. . . . . . . . . . . . . . . . . . . . . 571
22-4 OnCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
22-5 Low-Level (OnCE) Tap Module Data Registers (DRs) . . . . . . 580
22-6 OnCE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
22-7 OnCE Controller and Serial Interface . . . . . . . . . . . . . . . . . . .585
Freescale Semiconductor, Inc.
For More Information On This Product,
TAP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Go to: www.freescale.com
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