MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 414

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Serial Peripheral Interface Module (SPI)
18.8.1 Master Mode
Advance Information
414
Setting the MSTR bit in SPICR1 puts the SPI in master mode. Only a
master SPI can initiate a transmission. Writing to the master SPIDR
begins a transmission. If the shift register is empty, the byte transfers to
the shift register and begins shifting out on the MOSI pin under the
control of the master SCK clock. The SCK clock starts one-half SCK
cycle after writing to SPIDR.
The SPR[2:0] and SPPR[6:4] bits in SPIBR control the baud rate
generator and determine the speed of the shift register. The SCK pin is
the SPI clock output. Through the SCK pin, the baud rate generator of
the master controls the shift register of the slave.
The MSTR bit in SPICR1 and the SPC0 bit in SPICR2 control the
function of the data pins, MOSI and MISO.
The SS pin is normally an input that remains in the inactive high state.
Setting the DDRSP3 bit in SPIDDR configures SS as an output. The
DDRSP3 bit and the SSOE bit in SPICR1 can configure SS for
general-purpose I/O, mode fault detection, or slave selection.
See
The SS output goes low during each transmission and is high when the
SPI is in the idle state. Driving the master SS input low sets the MODF
flag in SPISR, indicating a mode fault. More than one master may be
trying to drive the MOSI and SCK lines simultaneously. A mode fault
clears the data direction bits of the MISO, MOSI (or MOMI), and SCK
pins to make them inputs. A mode fault also clears the SPE and MSTR
bits in SPICR1. If the SPIE bit is also set, the MODF flag generates an
interrupt request.
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
18-3.
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA