MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 475

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

19.9.3.2 Conversion Cycle Times
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Total conversion time is made up of initial sample time, final sample time,
and resolution time. Initial sample time refers to the time during which the
selected input channel is coupled through the sample buffer amplifier to
the sample capacitor. The sample buffer is used to quickly reproduce its
input signal on the sample capacitor and minimize charge sharing errors.
During the final sampling period the amplifier is bypassed, and the
multiplexer input charges the sample capacitor array directly for
improved accuracy. During the resolution period, the voltage in the
sample capacitor is converted to a digital value and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be
2, 4, 8, or 16 QCLK cycles, depending on the value of the IST field in the
CCW. Resolution time is 10 QCLK cycles.
A conversion requires a minimum of 14 QCLK cycles (7 s with a
2.0-MHz QCLK). If the maximum final sample time period of 16 QCLKs
is selected, the total conversion time is 28 QCLKs or 14 s (with a
2.0-MHz QCLK).
If the amplifier bypass mode is enabled for a conversion by setting the
amplifier bypass (BYP) field in the CCW, the timing changes to that
shown in
Table (CCW)
time is eliminated, reducing the potential conversion time by two QCLKs.
When using the bypass mode, the external circuit should be of low
source impedance (typically less than 10 k ). Also, the loading effects
on the external circuitry of the QADC need to be considered, because
the benefits of the sample amplifier are not present.
QCLK
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
2 CYCLES
BUFFER
SAMPLE
TIME:
Figure
SAMPLE TIME
Go to: www.freescale.com
for more information on the BYP field. The initial sample
N CYCLES
(2,4,8,16)
SAMPLE
19-21. See
FINAL
TIME:
Figure 19-20. Conversion Timing
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
19.8.7 Conversion Command Word
Queued Analog-to-Digital Converter (QADC)
RESOLUTION
10 CYCLES
TIME:
Functional Description
Advance Information
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