MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 167

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.4 Microarchitecture Summary
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
DATA CALCULATION
WRITEBACK BUS
SIGN EXT.
GENERAL-PURPOSE
REGISTER FILE
X PORT
32 BITS X 16
ADDER/LOGICAL PRIORITY ENCODER/
MUX
ZERO DETECT RESULT MUX
BARREL SHIFTER
REGISTER FILE
Figure 7-1. M•CORE Processor Block Diagram
ALTERNATE
32 BITS X 16
MULTIPLIER
Figure 7-1
The processor utilizes a 4-stage pipeline for instruction execution. The
instruction fetch, instruction decode/register file read, execute, and
register file writeback stages operate in an overlapped fashion, allowing
single clock instruction execution for most instructions.
The execution unit consists of a 32-bit arithmetic/logic unit (ALU), a
32-bit barrel shifter, a find-first-one unit, result feed-forward hardware,
support hardware for multiplication and division, and multiple-register
load and store instructions.
DIVIDER
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
H/W ACCELERATOR INTERFACE BUS
Y PORT
is a block diagram of the M•CORE processor.
MUX
REGISTER FILE
Go to: www.freescale.com
SCALE
32 BITS X 13
CONTROL
IMMEDIATE
MUX
DATA
BUS
M•CORE M210 Central Processor Unit (CPU)
INCREMENT
ADDRESS GENERATION
INSTRUCTION PIPELINE
INSTRUCTION DECODE
PC
ADDRESS MUX
Microarchitecture Summary
BRANCH
ADDER
Advance Information
ADDRESS
BUS
167