MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 453

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

19.8.6 Status Registers
19.8.6.1 QADC Status Register 0 (QASR0)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00ca_0010 and 0x00ca_0011
Reset:
Reset:
Read:
Read:
Write:
Write:
This subsection describes the QADC status registers.
QADC Status Register 0 (QASR0) contains information about the state
of each queue and the current A/D conversion.
Stop mode resets this register ($0000).
Read: Anytime
Write:
CF1 — Queue 1 Completion Flag
For flag bits (CF1, PF1, CF2, PF2, TOR1, TOR2): Writing a 1 has no
effect, write a 0 to clear.
For QS[9:6] and CWP: Writes have no effect.
CF1 indicates that a queue 1 scan has been completed. CF1 is set by
the QADC when the input channel sample requested by the last CCW
in queue 1 is converted, and the result is stored in the result table.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Bit 15
Bit 7
QS7
CF1
0
0
Figure 19-11. QADC Status Register 0 (QASR0)
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
QS6
PF1
14
0
6
0
CWP5
CF2
13
0
5
0
CWP4
PF2
12
0
4
0
Queued Analog-to-Digital Converter (QADC)
CWP3
TOR1
11
0
3
0
CWP2
TOR2
10
0
2
0
Register Descriptions
Advance Information
CWP1
QS9
9
0
1
0
CWP0
Bit 8
QS8
Bit 0
0
0
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