MMC2114 MOTOROLA [Motorola, Inc], MMC2114 Datasheet - Page 163

• Manufacturer Part Number: MMC2114
• Description: M CORE Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

6.4.14 Timers (TIM1 and TIM2)
6.5 Summary of Peripheral State During Low-Power Modes
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
In stop mode (or doze mode, if so programmed), the SCIs stop
immediately and freeze their operation, register values, state machines,
and external pins. During these modes, the SCI clocks are shut down.
Coming out of the doze or stop modes, returns the SCIs to operation
from the state prior to the low-power mode entry.
When not stopped, the timers may generate an interrupt to exit the
low-power modes.
Clearing the timer enable bit (TE) in the Timer System Control Register 1
(TIMSCR1) or the pulse accumulator enable bit (PAE) in the Pulse
Accumulator Control Register (TIMPACTL) disables timer functions.
Timer and pulse accumulator registers are still accessible by the CPU
and OnCE interface, but the remaining functions of the timer are
disabled. See
Pulse Accumulator Control
The timer is unaffected by either the wait or doze modes and may
generate an interrupt to exit these modes.
In stop mode, the timers stop immediately and freeze their operation,
register values, state machines, and external pins. Upon exiting stop
mode, the timer will resume operation unless stop mode was exited by
reset.
The functionality of each of the peripherals and CPU during the various
low-power modes is summarized in
peripheral during a given mode refers to the condition the peripheral
automatically assumes when the particular instruction (WAIT, DOZE, or
STOP) is executed. Individual peripherals may be disabled by
programming its dedicated control bits. The wakeup capability field
refers to the ability of an interrupt or reset by that peripheral to force the
CPU into run mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
16.7.6 Timer System Control Register 1
Power Management
Summary of Peripheral State During Low-Power Modes
Register.
Table
6-1. The status of each
Advance Information
Power Management
and
16.7.15
163